Datasheet

Section 24 A/D Converter
Page 820 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
24.2.1 A/D Data Registers 0 to 7 (ADDR0 to ADDR7)
b15
0
b14
0
b13
0
b12
0
b11
0
b10
0
b9
0
b8
0
H'FF05E0 to H'FF05EE, H'FF0600 to H'FF0606
b7
0
b6
0
b5
−
0
b4
−
0
b3
−
0
b2
−
0
b1
−
0
b0
−
0
Address:
Bit:
Value after reset:
ADDR registers are 16-bit read-only registers which are used to store the results of A/D
conversion. Unit 1 incorporates eight registers ADDR0 to ADDR7. Unit 2 incorporates four
registers ADDR0_2 to ADDR3_2. The ADDR registers, which store a conversion result for each
channel, are shown in table 24.2.
The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0.
The data bus between the CPU and the A/D converter is 16-bit width. Data can be accessed in 16
bits at one time or 8 bits at two times.
Table 24.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Channel Set 0 (CH3 = 0) Channel Set 1 (CH3 = 1)
A/D Data Register which
Stores Conversion Result
AN0 AN8 ADDR0
AN1 AN9 ADDR1
AN2 AN10 ADDR2
AN3 AN11 ADDR3
AN4 ⎯ ADDR4
AN5 ⎯ ADDR5
AN6 ⎯ ADDR6
AN7 ⎯ ADDR7