Datasheet

Section 24 A/D Converter
REJ09B0465-0300 Rev. 3.00 Page 817 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
+
AN0_2
AN1_2
AN2_2
AN3_2
ADTRG2
ADTRG1
AVcc
AVss
ADDR0_2/CMPR_2
ADDR1_2/CMPCSR_2 ADDR2_2/CMPVALH_2
ADDR3_2/CMPVALL_2
ADMR_2
ADCSR_2
ADCR_2
Module data bus
Internal data bus
Bus interface
CMPI interrupt signal
AD interrupt signal
Conversion start trigger from timer RC or RD
Sample-and-hold circuit
Comparator
10-bit D/A
Successive aproximations register
Multiplexer
Control circuit
Figure 24.2 Block Diagram of A/D Converter (Unit 2)