Datasheet

Section 23 Hardware LIN
REJ09B0465-0300 Rev. 3.00 Page 809 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Timer RA
Start pulse width measurement by setting the TSTART
bit in the TRACR register to 1.
Timer RA
Read the count status flag (TCSTF) from the TRACR
register.
Hardware LIN
Start Sync Break detection by setting the LSTART bit in the
LINCR register to 1.
Hardware LIN
Read the RXD input status flag (RXDSF) from the LINCR
register.
A
TCSTF = 1?
Yes
RXDSF = 1?
Yes
No
No
Wait until timer RA starts counting.
Wait until the RXD input to SCI3_1 is
masked by the hardware LIN.
After writing 1 to the LSTART bit,
do not input a low level to the RXD
pin until 1 is read from the RXDSF flag;
during this period, the low level input is
directly input to the SCI3_1. After 1 is
read from the RXDSF flag, input to
timer RA and SCI3_1 is possible.
Detect the hardware LIN Sync Break.
The timer RA interrupt can be used.
When Sync Break is detected, the timer
RA counter is reloaded with the initially
set value.
If the low level input is shorter than the
specified time, the timer RA counter is
also reloaded with the initially set value
and waits for another low level input.
When the SBE bit in the LINCR register
is 0 (the input mask is cancelled upon
Sync Break detection), timer RA can be
used in timer mode after the SBDCT flag
in the LINST register becomes 1.
Hardware LIN
Read the Sync Break detection flag (SBDCT) from the
LINST register.
SBDCT = 1?
Yes
No
B
Hardware LIN
Enable/disable the interrupts (bus conflict detection,
Sync Break detection, and Sync Field measurement
end) by setting the BCIE, SBIE, and SFIE bits in the
LINCR register.
Figure 23.7 Header Field Reception Flowchart (2)