Datasheet

Section 23 Hardware LIN
Page 806 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
23.3.2 Slave Mode
Figure 23.5 shows the example of hardware LIN interface operation for receiving the header field
in slave mode. Figures 23.6 to 23.8 show the flowcharts for header field reception.
The hardware LIN interface operates as follows for header field reception.
1. When 1 is written to the LSTART bit in LINCR register of the hardware LIN interface, Sync
Break detection is enabled.
2. When a low level input is longer than the time set in timer RA, it is detected as Sync Break,
thus setting the SBDCT flag in the LINST register to 1. In this case, if the SBIE bit in the
LINCR register is set to 1, the timer RA/HW-LIN interrupt occurs. The hardware LIN
interface then measures the Sync Field.
3. The hardware LIN interface receives the Sync Field (H'55). During reception, the hardware
LIN interface measures the time from the start bit through bit 6. Here, the Sync Field input to
the SCI3 RXD can be either enabled or disabled depending on the SBE bit setting in the
LINCR register.
4. Completion of Sync Field measurement sets the SFDCT flag in the LINST register to 1. In this
case, if the SFIE bit in the LINCR register is 1, the timer RA/HW-LIN interrupt occurs.
5. After completing Sync Field measurement, the hardware LIN interface calculates the transfer
rate from the timer RA count value and sets the rate in SCI3_1, and also updates the TRAPRE
and TRATR registers in timer RA. Then the hardware LIN interface receives the ID field using
SCI3_1.
6. After completing ID field reception, the hardware LIN interface performs response field
communications.