Datasheet

Section 23 Hardware LIN
REJ09B0465-0300 Rev. 3.00 Page 805 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Timer RA
Start the timer counter by setting the TSTART bit in the
TRACR register to 1.
Timer RA
Read the count status flag (TCSTF) from the TRACR register.
Hardware LIN
Read the Sync Break detection flag (SBDCT) from the LINST
register.
Timer RA
Read the Sync Break detection flag (SBDCT) from the LINST
register.
Timer RA
Stop the timer counter by setting the TSTART bit in the
TRACR register to 0.
SCI3_1
Initialize SCI3_1 and set asynchronous mode, transmission,
and clock source by setting the SCR3, SMR, and BRR
registers.
The timer RA interrupt can be used
upon completion of Sync Break
generation.
Transmit the ID field.
A
TCSTF = 1?
SBDCT = 1?
Yes
TCSTF = 0?
Yes
SCI3_1
Perform communications using SCI3_1.
Transfer the ID field to TDR register.
No
Yes
No
No
After writing 0 to the TSTART bit,
reading 0 from the TCSTF flag can
be omitted if neither TRAPRE register
nor TRATR register of timer RA is
read or modified.
Initialize SCI3 following the initialization
procedure and set the appropriate clock
source for Sync Field transmission.
SCI3_1
Perform communications using SCI3_1.
Read 1 from the TDRE bit in the SSR register.
Transfer H'55 to TDR register.
Transmit the Sync Field.
After generating timer RA Sync Break,
stop the timer counter.
Generate Sync Break by timer RA.
After writing 1 to the TSTART bit,
reading 1 from the TCSTF flag can
be omitted if neither TRAPRE register
nor TRATR register of timer RA is
read or modified.
Figures 23.4 Header Field Transmission Flowchart (2)