Datasheet

Section 23 Hardware LIN
Page 800 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Table 23.1 shows the hardware LIN pins.
Table 23.1 Pin Configuration
Pin Symbol I/O Description
RXD Input Receive-data input to the hardware LIN
TXD Output Transmit-data output from the hardware LIN
23.2 Register Configuration
The hardware LIN interface has the following registers.
• LIN control register (LINCR)
• LIN status register (LINST)
23.2.1 LIN Control Register (LINCR)
Address:
Bit:
Value after reset:
b7
LINE
0
b6
MST
0
b5
SBE
0
b4
LSTART
0
b3
RXDSF
0
b2
BCIE
0
b1
SBIE
0
b0
SFIE
0
H'FF0518
Bit Symbol Bit Name Description R/W
7 LINE LIN start 0: Enables LIN operation.
1: Disables LIN operation.*
1
R/W
6 MST LIN operating
mode setting*
2
0: Slave mode (Enables the Sync Break detector.)
1: Master mode (Takes the OR between timer RA
output and TXD data.)
R/W
5 SBE RXD input
mask
cancellation
timing select
(Valid only in slave mode)
0: Cancels the mask upon Sync Break detection.
1: Cancels the mask upon completion of Sync Field
measurement.
R/W