Datasheet

Section 22 Synchronous Serial Communication Unit (SSU)

REJ09B0465-0300 Rev. 3.00 Page 797 of 982

Sep 17, 2010

H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group

22.3.7 SCS Pin Control and Arbitration

When the SSUMS bit in SSMR2 is set to 1 and the CSS1 bit is set to 1, the MSS bit in SSCRH is

set to 1 and then the arbitration of the SCS pin is checked before starting serial transfer. If the SSU

detects that the synchronized internal SCS pin goes low in this period, the CE bit in SSSR is set

and the MSS bit in SSCRH is cleared.

Note: When a conflict error is set, subsequent transmit operation is not possible. Therefore the

CE bit must be cleared to 0 before starting transmission.

When the multimaster error is used, the CSOS bit in SSMR2 should be set to 1.

MSS

Transfer start

Write data

in SSTDR

Arbitration detection

period

Maximum time of SCS internal synchronization

Internal SCS

(synchronized)

SCS input

SCS output

(Hi-Z)

Figure 22.13 Arbitration Check Timing