Datasheet

Section 22 Synchronous Serial Communication Unit (SSU)
Page 782 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
22.3.3 Relationship between Data Input/Output Pin and Shift Register
Relationship of connection between the data input/output pin and SSTRSR changes according to a
combination of the MSS bit in SSCRH and the SSUMS bit in SSMR2. It also changes by the
BIDE bit in SSMR2. Figure 22.3 shows the relationship.
SSO
Shift register
(SSTRSR)
Shift register
(SSTRSR)
Shift register
(SSTRSR)
Shift register
(SSTRSR)
(1) When SSUMS = 0:
(3) When SSUMS = 1, BIDE = 0, and MSS = 0:
(2) When SSUMS = 1, BIDE = 0, and MSS = 1:
(4) When SSUMS = 1 and BIDE = 1:
SSI
SSO
SSI
SSO
SSI
SSO
SSI
Figure 22.3 Relationship between Data Input/Output Pin and Shift Register