Datasheet

Section 22 Synchronous Serial Communication Unit (SSU)
REJ09B0465-0300 Rev. 3.00 Page 781 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
22.3 Operation
22.3.1 Transfer Clock
Transfer clock can be selected from seven internal clocks and an external clock. When this module
is used, the SSCK pin must be selected as a serial clock by setting the SCKS bit in SSMR2 to 1.
When the MSS bit in SSCRH is 1, an internal clock is selected and the SSCK pin is in the output
state. If transfer is started, the SSCK pin outputs clocks of the transfer rate set in the CKS2 to
CKS0 bits in SSCRH. When the MSS bit is 0, an external clock is selected and the SSCK pin is in
the input state.
22.3.2 Relationship between Clock Polarity and Phase, and Data
Relationship between clock polarity and phase, and transfer data changes according to a
combination of the SSUMS bit in SSMR2 and the CPOS and CPHS bits in SSMR. Figure 22.2
shows the relationship.
MSB-first transfer or LSB first transfer can be selected by the setting of the MLS bit in SSMR.
When the MLS bit is 1, transfer is started from LSB to MSB. When the MLS bit is 0, transfer is
started from MSB to LSB.
SSCK
(1) When CPHS = 0, CPOS =0, and SSUMS = 0:
(2) When CPHS = 0 and SSUMS = 1:
(3) When CPHS = 1 and SSUMS = 1:
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSO, SSI
SSO, SSI
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSO, SSI
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
SCS
SCS
Figure 22.2 Relationship between Clock Polarity and Phase, and Data