Datasheet

Section 22 Synchronous Serial Communication Unit (SSU)
REJ09B0465-0300 Rev. 3.00 Page 773 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
22.2.4 SS Mode Register (SSMR)
Address:
Bit:
Value after reset:
b7
MLS
0
b6
CPOS
0
b5
CPHS
0
b4
⎯
1
b3
⎯
1
b2
0
b1
BC[2:0]
0
b0
0
H'FF05CA
Bit Symbol Bit Name Description R/W
7 MLS MSB-first/LSB-
first select
0: Transfer by MSB-first
1: Transfer by LSB-first
R/W
6 CPOS Clock polarity
select
0: SSCK clock idling state = high
1: SSCK clock idling state = low
R/W
5 CPHS Clock phase
select
0: Data change at first edge
1: Data latch at first edge
R/W
4, 3 ⎯ Reserved This bit is read as 1. The write value should be 1. ⎯
2 to 0 BC[2:0] Bit counter 2 to
0
000: 8 bits
001: 1 bit
010: 2 bits
011: 3 bits
100: 4 bits
101: 5 bits
110: 6 bits
111: 7 bits
R/W
• BC[2:0] bits (bit counter 2 to 0)
When read, the remaining number of transfer bits is indicated.