Datasheet

Section 21 I
2
C Bus Interface 2 (IIC2)
REJ09B0465-0300 Rev. 3.00 Page 765 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
21.6 Usage Notes
21.6.1 SCL and SDA pins selected by PMC
This LSI incorporates the IIC2 and SSU modules, one of which module functions should be
selected by the SELICSU bit in ICSUSR. Therefore, when assigning the pin functions using the
peripheral function mapping controller (PMC), the SCL and SDA pin functions should be
assigned to the P56 and P57 pins when the IIC2 function is selected. If these pin functions are
assigned to other pins, correct operation cannot be guaranteed.
21.6.2 Restriction on Use of Bit Manipulation Instructions to Set MST and TRS in Multi-
Master Usage
When master transmission is selected by consecutively manipulating the MST and TRS bits in
multi-master usage, an arbitration loss during execution of the bit-manipulation instruction for
TRS leads to the contradictory situation where AL in ICSR is 1 in master transmit mode
(MST = 1, TRS = 1).
Ways to avoid this effect are listed below.
• Use the MOV instruction to set MST and TRS when used in multi-master mode.
• When arbitration is lost, confirm that MST = 0 and TRS = 0. If the setting of MST = 0 and
TRS = 0 is not confirmed, then set MST = 0 and TRS = 0 again.
21.6.3 Note regarding Master Receive Mode of I
2
C-Bus Interface Mode
When the interface is used with the I
2
C bus format in master receive mode, an overlap between
issuing of the stop condition or re-issuing of the start condition and the falling edge of the ninth
cycle of the SCL signal leads to output of the tenth cycle of SCL.
To avoid this problem, after a master receive operation is completed, confirm the falling edge of
the ninth clock cycle of the SCL signal and generate a stop condition or regenerate a start
condition.
• After confirming that the receive data register full (RDRF) flag in the ICSR has become one,
confirm that the SCL output level monitor (SCLO) bit in ICCR2 has become zero (indicating
low-level output on the SCL pin).