Datasheet

Section 21 I
2
C Bus Interface 2 (IIC2)
REJ09B0465-0300 Rev. 3.00 Page 763 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
21.4 Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK detection, STOP condition detection, and arbitration lost/overrun error. Table 21.3 shows
the contents of each interrupt request.
Table 21.3 Interrupt Requests
Interrupt Request Abbreviation Interrupt Condition I
2
C Mode
Clock
Synchronous
Mode
Transmit Data Empty TXI (TDRE=1)
•
(TIE=1) O O
Transmit End TEI (TEND=1)
•
(TEIE=1) O O
Receive Data Full RXI (RDRF=1)
•
(RIE=1) O O
STOP Condition Detection STPI (STOP=1)
•
(STIE=1) O ×
NACK Detection O ×
Arbitration Lost/
Overrun Error
NAKI {(NACKF=1)+(AL=1)}
•
(NAKIE=1)
O O
When an exception processing is executed under interrupt conditions described in table 21.3,
interrupt sources should be cleared in the exception processing. TDRE and TEND are
automatically cleared to 0 by writing the transmit data to ICDRT. RDRF are automatically cleared
to 0 by reading ICDRR. TDRE is set to 1 again at the same time when transmit data is written to
ICDRT. When TDRE is cleared to 0, then an excessive data of one byte may be transmitted.
The DTC can be activated by a TXI interrupt request to transfer data. The TDRE flag is
automatically cleared upon data transfer by the DTC. The DTC can also be activated by an RXI
interrupt request to transfer data. The RDRF flag is automatically cleared to 0 upon data transfer
by the DTC.