Datasheet

Section 21 I
2
C Bus Interface 2 (IIC2)
Page 758 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
21.3.7 Noise Filter Circuit
The signal state on the SCL and SDA pins are internally latched via the noise filter circuit. Figure
21.16 shows a block diagram of the noise filter circuit.
The noise filter consists of two cascaded latches and a match detector. The SCL (or SDA) input
signal is sampled on the system clock. When both outputs of the latches match, its level is output
to other blocks by the match detector circuit. If they do not match, the previous value is held.
C
QD
Match detector
circuit
Internal
SCL or SDA
signal
SCL or SDA
input signal
Sampling
clock
Sampling clock
System clock
cycle
Latch
Latch
C
Q
D
Figure 21.16 Block Diagram of Noise Filter Circuit