Datasheet

Section 21 I
2
C Bus Interface 2 (IIC2)
REJ09B0465-0300 Rev. 3.00 Page 755 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
ICDRS
ICDRR
12345678 99
A
A
RDRF
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
SCL
(Slave output)
User
processing
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 1
[3] Set ACKBT
[3] Read ICDRR
[4] Read ICDRR
Data 2
Data 1
Figure 21.12 Slave Receive Mode Operation Timing (2)
21.3.6 Clock Synchronous Serial Format
This module can be operated with the clock synchronous serial format by setting the FS bit in
SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When
MST is 0, the external clock input is selected.
(1) Data Transfer Format
Figure 21.13 shows the clock synchronous serial transfer format.
The transfer data is output from the rise to the fall of the SCL clock, and the data at the rising edge
of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer: in either the
MSB first or LSB first. The output level of SDA can be changed during the transfer wait by the
SDAO bit in ICCR2.
SDA
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
SCL
Figure 21.13 Clock Synchronous Serial Transfer Format