Datasheet

Section 21 I
2
C Bus Interface 2 (IIC2)
Page 754 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
21.3.5 Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, see figures
21.11 and 21.12. The reception procedure and operations in slave receive mode are described
below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the
read data show the slave address + R/W, it is not used.)
3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is set to 1,
SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR,
which is returned to the master device, is reflected to the next transmit frame.
4. The last byte data is read by reading ICDRR.
ICDRS
ICDRR
12 1345678 99
A
A
RDRF
Data 1 Data 2
Data 1
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
SCL
(Slave output)
Bit 7 Bit 7Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[2] Read ICDRR (dummy read)
[2] Read ICDRR
User
processing
Figure 21.11 Slave Receive Mode Operation Timing (1)