Datasheet

Section 21 I
2
C Bus Interface 2 (IIC2)
REJ09B0465-0300 Rev. 3.00 Page 741 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
21.2.6 I
2
C Bus Status Register (ICSR)
Address:
Bit:
Value after reset:
b7
TDRE
0
b6
TEND
0
b5
RDRF
0
b4
NACKF
0
b3
STOP
0
b2
AL_OVE
0
b1
AAS
0
b0
ADZ
0
H'FF05CC
Bit Symbol Bit Name Description R/W
7 TDRE Transmit data
empty flag
[Setting conditions]
• When data is transferred from ICDRT to ICDRS
and ICDRT becomes empty
• When TRS is set
• When a start condition (including re-transfer) has
been issued
• When transmit mode is entered from receive
mode in slave mode
• When 1 is written to IICRST in ICCR2 in master
transmit mode and slave transmit mode
[Clearing conditions]
• When 0 is written in TDRE after reading
TDRE = 1
• When data is written to ICDRT with an instruction
• When the DTC transfers data to ICDRT by a TXI
interrupt request, and the DTC settings satisfy
the flag clearing conditions.
R/W
6 TEND Transmit end flag [Setting conditions]
• When the ninth clock of SCL rises with the I
2
C
bus format while the TDRE flag is 1
• When the final bit of transmit frame is sent with
the clock synchronous serial format
[Clearing conditions]
• When 0 is written in TEND after reading
TEND = 1
• When data is written to ICDRT with an instruction
R/W