Datasheet

Section 21 I
2
C Bus Interface 2 (IIC2)
REJ09B0465-0300 Rev. 3.00 Page 739 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
21.2.5 I
2
C Bus Interrupt Enable Register (ICIER)
Address:
Bit:
Value after reset:
b7
TIE
0
b6
TEIE
0
b5
RIE
0
b4
NAKIE
0
b3
STIE
0
b2
ACKE
0
b1
ACKBR
0
b0
ACKBT
0
H'FF05CB
Bit Symbol Bit Name Description R/W
7 TIE Transmit
interrupt enable
0: Transmit data empty interrupt request (TXI) is
disabled.
1: Transmit data empty interrupt request (TXI) is
enabled.
R/W
6 TEIE Transmit end
interrupt enable
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
R/W
5 RIE Receive
interrupt enable
0: Receive data full interrupt request (RXI) is
disabled.
1: Receive data full interrupt request (RXI) is
enabled.
R/W
4 NAKIE NACK receive
interrupt enable
0: NACK receive interrupt request (NAKI) and
overrun error interrupt request (ERI) with the
clock synchronous format are disabled.
1: NACK receive interrupt request (NAKI) and
overrun error interrupt request (ERI) with the
clock synchronous format are enabled.
R/W
3 STIE Stop condition
detection
interrupt enable
0: Stop condition detection interrupt request (STPI)
is disabled.
1: Stop condition detection interrupt request (STPI)
is enabled.
R/W
2 ACKE Acknowledge
bit judgment
select
0: The value of the receive acknowledge bit is
ignored, and continuous transfer is performed.
1: If the receive acknowledge bit is 1, continuous
transfer is stopped.
R/W
1 ACKBR Receive
acknowledge
0: Receive acknowledge = 0
1: Receive acknowledge = 1
R
0 ACKBT Transmit
acknowledge
0: 0 is sent at the acknowledge timing.
1: 1 is sent at the acknowledge timing.
R/W