Datasheet

Section 21 I
2
C Bus Interface 2 (IIC2)
REJ09B0465-0300 Rev. 3.00 Page 737 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
21.2.4 I
2
C Bus Mode Register (ICMR)
Address:
Bit:
Value after reset:
b7
MLS
0
b6
WAIT
0
b5
⎯
0
b4
⎯
1
b3
BCWP
1
b2
0
b1
0
b0
0
H'FF05CA
BC[2:0]
Bit Symbol Bit Name Description R/W
7 MLS MSB-first/LSB-
first select
0: Transfer in MSB-first*
1: Transfer in LSB-first
R/W
6 WAIT Wait insertion 0: Data and acknowledge bits are transferred
consecutively with no wait inserted.
1: After the fall of the clock for the final data bit, low
period is extended for two transfer clocks.
R/W
5 ⎯ Reserved This bit is read as 0. The write value should be 0. ⎯
4 ⎯ Reserved This bit is read as 1. The write value should be 1. ⎯
3 BCWP BC write
protect
0: When writing, modifying BC2 to BC0 values is
valid.
1: When writing, modifying BC2 to BC0 values is
invalid.
R/W
2 to 0 BC[2:0] Bit counter 2 to
0
I
2
C Bus Format Clock Synchronous Serial Format
000: 9 bits 000: 8 bits
001: 2 bits 001: 1 bits
010: 3 bits 010: 2 bits
011: 4 bits 011: 3 bits
100: 5 bits 100: 4 bits
101: 6 bits 101: 5 bits
110: 7 bits 110: 6 bits
111: 8 bits 111: 7 bits
R/W
Note: * Set this bit to 0 when the I
2
C bus format is used.