Datasheet

Section 21 I
2
C Bus Interface 2 (IIC2)
REJ09B0465-0300 Rev. 3.00 Page 733 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
21.2.2 I
2
C Bus Control Register 1 (ICCR1)
Address:
Bit:
Value after reset:
b7
ICE
0
b6
RCVD
0
b5
MST
0
b4
TRS
0
b3
0
b2
0
b1
0
b0
0
H'FF05C8
CKS[3:0]
Bit Symbol Bit Name Description R/W
7 ICE I
2
C bus
interface 2
enable
0: This module is stopped. (SCL and SDA pins are
set to port function.)
1: This bit is enabled for transfer operations. (SCL
and SDA pins are bus drive state.)
R/W
6 RCVD Reception
disable
0: Enables next reception
1: Disables next reception
R/W
5 MST Master/slave
select
R/W
4 TRS Transmit/
receive select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
R/W
3 to 0 CKS[3:0] Transfer clock
select 3 to 0
These bits should be set according to the necessary
transfer rate (see table 21.2) in master mode.
R/W
• RCVD bit (reception disable)
Selects to enable or disable the next operation when TRS is 0 and ICDRR is read.
• MST bit (master/slave select) and TRS bit (transmit/receive select)
In master mode with the I
2
C bus format, when arbitration is lost, MST and TRS are both reset
by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be
performed between transfer frames.
After data receive has been started in slave receive mode, when the first seven bits of the
receive data agree with the slave address that is set to SAR and the eighth bit is 1, TRS is
automatically set to 1. If an overrun error occurs in master mode with the clock synchronous
serial format, MST is cleared to 0 and slave receive mode is entered.
Operating modes are described above according to MST and TRS combination. When clock
synchronous serial format is selected and MST is 1, clock is output.