Datasheet
Section 21 I
2
C Bus Interface 2 (IIC2)
REJ09B0465-0300 Rev. 3.00 Page 729 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Section 21 I
2
C Bus Interface 2 (IIC2)
The I
2
C bus interface 2 conforms to and provides a subset of the Philips I
2
C bus (inter-IC bus)
interface functions. The register configuration that controls the I
2
C bus differs partly from the
Philips configuration, however. Figure 21.1 shows a block diagram of the I
2
C bus interface 2.
Figure 21.2 shows an example of I/O pin connections to external circuits.
Either the IIC2 or SSU incorporated in this LSI can be used at a time. Accordingly, when the IIC2
function is used, the SSU function is not available.
21.1 Features
• Selectable for I
2
C bus format or clock synchronous serial format
• Continuous transmission/reception
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
I
2
C Bus Format:
• Start and stop conditions generated automatically in master mode
• Selectable for acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function stored
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically. If transmission/reception is not yet possible, set the SCL to low until
preparations are completed.
• Six interrupt sources
Transmit data empty (including slave-address match), transmit end, receive data full (including
slave-address match), arbitration lost, NACK detection, and stop condition detection. The DTC
can be activated by the transmit-data-empty and receive-data-full interrupts.
• Direct bus drive possible
Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive
function is selected.
Clock Synchronous Format:
• Four interrupt sources
Transmit-data-empty, transmit-end, receive-data-full, and overrun error. The DTC can be
activated by the transmit-data-empty and receive-data-full interrupt sources.