Datasheet

Section 20 Serial Communication Interface 3 (SCI3, IrDA)
REJ09B0465-0300 Rev. 3.00 Page 723 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
20.7 Noise Canceler
Figure 20.21 shows a block diagram of the noise canceler circuit. When the noise canceler
function is enabled, the RXD input signal is routed through the noise canceler before being
provided internally. The noise canceler consists of three cascaded latches and a match detector.
The RXD input signal is sampled at the basic clock frequency, 16 times the transfer rate, and when
the outputs of three latches agree, the level is passed to the next circuit. If they do not agree, the
previous value is held.
In other words, if the input level changes and the level remains the same for three or more clock
cycles after the change, it is recognized as a signal. However, if the level remains the same for less
than three clock cycles, it is recognized as a noise, not as a signal.
RXD
input signal
Internal
RXD signal
in figure 20.1
Sampling clock
Sampling clock
Internal basic clock
cycle
C
Latch
Q
D
C
Latch
Q
D
C
Latch
Q
D
Match
detector
circuit
SPMR
(NFEN)
Figure 20.21 Block Diagram of Noise Canceler