Datasheet

Section 20 Serial Communication Interface 3 (SCI3, IrDA)
REJ09B0465-0300 Rev. 3.00 Page 707 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
20.4.3 Data Transmission
Figure 20.10 shows an example of SCI3 operation for transmission in clocked synchronous mode.
In transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data
has been written to TDR, and transfers the data from TDR to TSR.
2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at
this time, a transmit data empty interrupt (TXI) is generated.
3. The SCI3 outputs eight synchronization clock pulses when clock output mode has been
specified. Data is output in synchronization with the input clock when use of an external clock
has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD
pin.
4. The SCI3 checks the TDRE flag at the timing for sending the MSB (bit 7).
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and transmission of the
next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the
output state of the MSB. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt request
is generated.
7. The SCK3 pin is fixed high at the end of transmission.
Figure 20.11 shows a sample flowchart for data transmission. Transmission will not start while a
receive error flag (OER, FER, or PER) is set to 1. Make sure that the receive error flags are
cleared to 0 before starting transmission.
Serial
clock
Serial
data
Bit 1Bit 0 Bit 7 Bit 0
1 frame 1 frame
Bit 1 Bit 6
Bit 7
TDRE
TEND
LSI
operation
User
processing
TXI interrupt request generated
Data written
to TDR
TDRE flag
cleared
to 0
TXI interrupt
request
generated
TEI interrupt request
generated
Figure 20.10 Example of Transmission in Clocked Synchronous Mode