Datasheet

Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Page 706 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
20.4 Operation in Clocked Synchronous Mode
Figure 20.9 shows the format for clocked synchronous communication. In clocked synchronous
mode, data is transmitted or received synchronous with clock pulses. A single character in the
transmit data consists of the 8-bit data starting from the LSB. In transmission, data is output from
one falling edge of the synchronization clock to the next. In reception, data is received in
synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the
transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor
bit is added. Inside the SCI3, the transmitter and receiver are independent units, enabling full-
duplex communication through the use of a common clock. Both the transmitter and the receiver
also have a double-buffered structure, so data can be read or written during transmission or
reception, enabling continuous data transfer.
Don’t care Don’t care
One unit of transfer data (character or frame)
8 bits
Bit 0
Serial data
Synchronization
clock
Bit 1 Bit 3 Bit 4 Bit 5
LSB
MSB
Bit 2 Bit 6 Bit 7
*
*
Note: * High except in continuous transfer
Figure 20.9 Data Format in Clocked Synchronous Communication
20.4.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM
bit in SMR and CKE0 and CKE1 bits in SCR3. When the SCI3 is operated on an internal clock,
the synchronization clock is output from the SCK3 pin. Eight synchronization clock pulses are
output in the transfer of one character, and when no transfer is performed the clock is fixed high.
20.4.2 SCI3 Initialization
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample
flowchart in figure 20.4.