Datasheet

Section 20 Serial Communication Interface 3 (SCI3, IrDA)
REJ09B0465-0300 Rev. 3.00 Page 699 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
20.3.2 SCI3 Initialization
Figure 20.4 shows a sample flowchart to initialize the SCI3. When the TE bit is cleared to 0, the
TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the
RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in
asynchronous mode, the clock must be supplied even during initialization.
Wait
<Initialization completion>
Start initialization
Set data transfer format in SMR.
[1]
Set TXD, RXD, and SCK3 pins by PMC.
Set CKE1 and CKE0 bits in SCR3.
No
Yes
Set value in BRR.
Clear TE and RE bits in SCR3 to 0.
[2]
[3]
Set TE and RE bits in SCR3 to 1,
and set RIE, TIE, TEIE, and MPIE bits.
Set PMR bit corresponding to TXD and
RXD pins to 1.
[4]
1-bit interval elapsed?
[1] With the PMC, select which of the TXD,
RXD, and SCK3 pins are to be used.
Set the clock selection in SCR3. Be sure
to clear the other bits in SCR3 to 0.
When clock output is selected in
asynchronous mode, after the CKE1 and
CKE0 settings have been made, output
of the clock signal begins immediately
upon setting of the PMR bits that
correspond to pins selected by SCK3.
When clock output is selected with
reception in clock-synchronous mode,
and CKE1, CKE0, and RE are set to 1,
output of the clock signal begins
immediately upon setting of the PMR bits
that correspond to pins selected by
SCK3.
[2] Set the data transfer format in SMR.
[3] Write the value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
[4] Wait at least one bit interval, then set the
TE bit or RE bit in SCR3 to 1.
For transmission, enable use of the TXD
output pin by setting the PMR bit for the
pin selected as TXD by the PMC to 1.
For reception, enable use of the RXD
input pin by setting the PMR bit for the
pin selected as RXD by the PMC to 1.
Also set the RIE, TIE, TEIE, and MPIE
bits, according to the required interrupts.
In asynchronous mode, SCI3 is in the
mark state (active) for transmission and
in the space state (idle) while waiting for
the start bit during reception. After the
TE bit has been set to 1 in the case of
transmission, transmission is enabled
after the output of a frame with all bits 1.
Figure 20.4 Sample Flowchart for Initializing SCI3