Datasheet

Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Page 690 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
20.2.8 Bit Rate Register (BRR)
Address:
Bit:
Value after reset:
b7
1
b6
1
b5
1
b4
1
b3
1
b2
1
b1
1
b0
1
H'FF0551, H'FF0559, H'FF0561
BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 20.3
shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0
SMR in asynchronous mode. Table 20.4 shows the maximum bit rate for each frequency in
asynchronous mode. The values shown in both tables 20.3 and 20.4 are values in active (high-
speed) mode. Table 20.5 shows of the relationship between the N setting in BRR and the n setting
in bits CKS1 and CKS0 of SMR in clocked synchronous mode. The values shown in table 20.5 are
values in active (high-speed) mode. The N setting in BRR and error for other operating
frequencies and bit rates can be obtained by the following formulas:
Note: The BRR value is retained in (module) standby mode.
[Asynchronous Mode]
N =
64 x 2
2n-1
x B
φ
-1
x 10
6
Error (%) =
(N + 1) x B x 64 x 2
2n-1
φ x 10
6
x 100
- 1
[Clocked Synchronous Mode]
N =
8 x 2
2n-1
x B
φ
-1
x 10
6
[Legend]
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n: CSK1 and CSK0 settings in SMR (0 ≤ n ≤ 3)