Datasheet

Section 20 Serial Communication Interface 3 (SCI3, IrDA)
REJ09B0465-0300 Rev. 3.00 Page 685 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
4 PM Parity mode (Enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
R/W
3 STOP Stop bit length (Enabled only in asynchronous mode)
0: 1 stop bit
1: 2 stop bits
R/W
2 MP Multiprocessor mode 0: The multiprocessor communication function is
disabled.
1: The multiprocessor communication function is
enabled*
2
R/W
1, 0 CKS[1:0] Clock select 0 and 1 00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/14 clock (n = 2)
11: φ/64 clock (n = 3)
R/W
Notes: 1. The SMR value is retained when (module) standby mode is entered.
2. In clocked synchronous mode, clear this bit to 0.
• STOP bit (stop bit length)
Selects the stop bit length in transmission. For reception, only the first stop bit is checked,
regardless of the value in the bit. If the second stop bit is 0, it is treated as the start bit of the
next transmit character.
• MP bit (multiprocessor mode)
When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit
and PM bit settings are invalid in multiprocessor mode.
• CKS[1:0] bits (clock select 1, 0)
These bits select the clock source for the baud rate generator.
For the relationship between the bit rate register setting and the baud rate, see section 20.2.8,
Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section
20.2.8, Bit Rate Register (BRR)).