Datasheet
Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Page 684 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
20.2.4 Transmit Data Register (TDR)
Address:
Bit:
Value after reset:
b7
1
b6
1
b5
1
b4
1
b3
1
b2
1
b1
1
b0
1
H'FF0553, H'FF055B, H'FF0563
TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is
empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-
buffered structure of TDR and TSR enables continuous transmission. If the next transmit data has
already been written to TDR during transmission of one-frame data, the SCI3 transfers the written
data to TSR to continue transmission. To achieve reliable serial transmission, write transmit data
to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to
H'FF.
20.2.5 Serial Mode Register (SMR)
Address:
Bit:
Value after reset:
b7
COM
0
b6
CHR
0
b5
PE
0
b4
PM
0
b3
STOP
0
b2
MP
0
b1
0
b0
0
H'FF0550, H'FF0558, H'FF0560
CKS[1:0]
Bit Symbol Bit Name Description R/W
7 COM Communication mode 0: Asynchronous mode
1: Clocked synchronous mode
R/W
6 CHR Character length (Enabled only in asynchronous mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length.
R/W
5 PE Parity enable (Enabled only in asynchronous mode)
0: Parity bit addition and parity check are
disabled.
1: The parity bit is added in transmission and the
parity bit is checked in reception.
R/W