Datasheet

Section 20 Serial Communication Interface 3 (SCI3, IrDA)

REJ09B0465-0300 Rev. 3.00 Page 683 of 982

Sep 17, 2010

H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group

20.2.1 Receive Shift Register (RSR)

Address:

Bit:

Value after reset:

⎯

RSR is a shift register that is used to receive serial data input from the RXD pin and convert it into

parallel data. When one frame of data has been received, it is transferred to RDR automatically.

RSR cannot be directly accessed by the CPU.

20.2.2 Receive Data Register (RDR)

Address:

Bit:

Value after reset:

H'FF0555, H'FF055D, H'FF0565

RDR is an 8-bit register that stores received data. When the SCI3 has received one frame of data,

it transfers the received data from RSR to RDR, where it is stored. After this, RSR is receive-

enabled. As RSR and RDR function as a double buffer in this way, continuous receive operations

are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR

cannot be written to by the CPU. RDR is initialized to H'00.

20.2.3 Transmit Shift Register (TSR)

Address:

Bit:

Value after reset:

⎯

TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first

transfers transmit data from TDR to TSR automatically, then sends the data that starts from the

LSB to the TXD pin

. TSR cannot be directly accessed by the CPU.