Datasheet

Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Page 680 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Clock
TXD
SCK3
TSR
RSR
Transmit/receive
control circuit
Internal data bus
Interrupt request
(TEI, TXI, RXI, ERI)
Internal clock (φ/64, φ/16, φ/4, φ)
External
clock
BRC
Baud rate generator
BRR
SMR
SCR3
SSR
TDR
RDR
RXD
SPMR
(1) SCI3 and SCI3_3
External
clock
Baud rate generator
BRC BRR
SMR
SCR3
SSR
TDR
RDR
RSR
SPMR
IrCR
Internal clock (φ/64, φ/16, φ/4, φ)
SCK3
RXD_2/IrRxD
TXD_2/IrTxD
TSR
Internal data bus
Transmit/receive
control circuit
Clock
Interrupt request
(TEI, TXI, RXI, ERI)
(2) SCI3_2
Figure 20.1 Block Diagram of SCI3