Datasheet

Section 19 Watchdog Timer (WDT)
REJ09B0465-0300 Rev. 3.00 Page 675 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
19.4 Usage Notes
19.4.1 Notes on System Design
While the watchdog timer is a useful function that restores the LSI to normal condition if the
system runs erratically for some reason, the watchdog timer may fail to be reset properly in
situations such as the perpetuation of an endless loop in a specific programming routine in which a
counter setting operation is executed. Also, there is a possibility of the watchdog timer not being
reset properly despite an erratic system condition if an interrupt is enabled and a counter value is
set within the interrupt processing.
These notes should be taken into consideration in the system design phases.
19.4.2 Notes on Stopping the Watchdog Timer or Switching the Count Clock
The MSTWDT bit in MSTCR1 is set to 1 after release from a reset, but the watchdog timer will
operate since φloco/8 is selected as the counter clock. (and, since the WDT is in module standby
mode, access to the registers is disabled). To stop the watchdog timer or switch the count clock,
proceed after releasing the WDT from module standby by clearing the MSTWDT bit in MSTCR1
to 0.