Datasheet

Section 19 Watchdog Timer (WDT)
Page 672 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
19.3 Operation
19.3.1 Watchdog Timer Overflow Reset
The watchdog timer is provided with an 8-bit counter. After a reset is released, TCWD starts
counting up. When the TCWD count value overflows H'FF, an internal reset signal is generated.
Since TCWD is a writable counter, it starts counting from the value set in TCWD. An overflow
period in the range of 1 to 256 input clock cycles can therefore be set, according to the TCWD set
value.
When the watchdog timer is not used, write 0 simultaneously to TMWLOCK and TMWI in
TCSRWD while the TCSRWE bit is 1 and set CKS[3:0] in TMWD to B'0111 (clock input
prohibited).
Figure 19.2 shows an example of watchdog timer operation.
Example: With 30-ms overflow period when φ = 4 MHz (selects φ/8192 for clock source)
4 x 10
6
x 30 x 10
–3
= 14.6
8192
TCWD overflow
H'FF
H'00
Internal reset signal
H'F1
TCWD
count value
H'F1 written to
TCWD
H'F1 written to TCWD
Reset generated
Therefore, 256 – 15 = 241 (H'F1) is set in TCWD.
Figure 19.2 Watchdog Timer Operation Example