Datasheet

Section 18 Timer RG
Page 664 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
18.3.6 Digital Filtering Function for Input Capture Inputs
Input signals on the TGIOA and TGIOB pins can be input via the digital filters. The digital filter
includes three latches connected in series and a matching detecting circuit. The input signals on
the TGIOA and TGIOB pins are operated on the sampling clock specified by the DFCK1 and
DFCK0 bits in TRGMDR. When outputs of the three latches match, the matching detecting circuit
outputs the signal level of the input. Otherwise, the output remains unchanged. That is, when a
pulse width is equal to or greater than three sampling clock cycles, the pulse is input as a signal.
When a pulse width is less than three sampling clock cycles, the pulse is considered as a noise to
be removed.
φ/32
φ/8
φ/4
φ/2
φ
φ
TPSC2 to
TPSC0
DFCK1 and
DFCK0
DFA and DFB
IOA[1:0] and
IOB[1:0]
Sampling clock
φ/32
φ/8
φ
Matching
detecting
circuit
Selecter
Edge
detecting
circuit
Sampling clock
TGIOA and TGIOB
input signal
C
Latch
DQ
C
Latch
DQ
C
Latch
DQ
C
Latch
D
Q
TGIOA and TGIOB
input signals
Digital-filtered signal
Cycle of a clock specified
by TPSC2 to TPSC0
or DFCK1 and DFCK0
Signal change is not output unless
signal levels match three times.
Signal propagation delay:
5 sampling clocks
C
Latch
D
Q
TCLKB
TCLKA
Figure 18.22 Block Diagram of Digital Filter