Datasheet

Section 18 Timer RG
REJ09B0465-0300 Rev. 3.00 Page 655 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
18.3.3 Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs (TCLKA and
TCLKB pins) is detected and TRGCNT is incremented/decremented accordingly.
When phase counting mode is set, the TCLKA and TCLK pins function as external clock input
pins and TRGCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to
TPSC0 and bits CKEG1 and CKEG0 in TRGCR.
(1) Example of Phase Counting Mode Setting Procedure
Figure 18.12 shows an example of the phase counting mode setting procedure.
Phase counting mode
Select phase counting mode
Start counting
<Phase counting mode>
Select phase counting mode with the MDF bit in TRGMDR.
[1]
[2]
[1]
[3]
[2]
Set the STR bit in TRGMDR to 1 to start the count
operation.
[2]
Select phase counting condition by setting TRGCNTCR.
Set phase counting condition
Figure 18.12 Example of Phase Counting Mode Setting Procedure