Datasheet

Section 18 Timer RG
Page 650 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Input-capture
input
φ
GRA, GRB
Input capture
signal
TRGCNT
N-1 N+1 N+2N
N
Figure 18.8 Input Capture Input Signal Timing
18.3.2 PWM Mode
In PWM mode, the PWM waveform is output from the TGIOA output pin by using GRA and
GRB as a pair. When an output pin is set for PWM mode, the TRGIOR output setting is ignored.
The high level output timing for PWM waveform is set in GRA and the low level output timing in
GRB.
Designating GRA or GRB compare match as the TRGCNT counter clearing source enables
outputting a PWM waveform in the range of 0% to 100% duty cycle from the TGIOA pin.
The correspondence between PWM output pins and registers is shown in table 18.4. When the
same value is set in GRA and GRB, the output value does not change even if a compare match
occurs.
Table 18.4 PWM Output Pins and Registers
Output Pin Output 1 Output 0
TGIOA GRA GRB
TGIOB Functions as general I/O port