Datasheet

Section 18 Timer RG
REJ09B0465-0300 Rev. 3.00 Page 647 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(c) Output compare output timing
A compare match signal is generated in the final state in which TRGCNT and GR match (the point
at which the count value matched by TRGCNT is updated). When a compare match signal is
generated, the output value set in TRGIOR is output at the output compare output pin (TGIOA,
TGIOB). After a match between TRGCNT and GR, the compare match signal is not generated
until the TRGCNT input clock is generated.
Figure 18.5 shows output compare output timing.
GRA , GRB
TRGCNT
TRGCNT
input clock
N
N
N + 1
Compare
match signal
TGIOA, TGIOB
φ
Figure 18.5 Output Compare Output Timing