Datasheet

Section 18 Timer RG
REJ09B0465-0300 Rev. 3.00 Page 641 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
18.2.8 General Registers A and B (GRA, GRB), GRA and GRB Buffer Registers
(BRA, BRB)
H'FF0642
GRA
H'FF0644
GRB
H'FF064C
BRA
H'FF064E
BRB
b15
1
b14
1
b13
1
b12
1
b11
1
b10
1
b9
1
b8
1
b7
1
b6
1
b5
1
b4
1
b3
1
b2
1
b1
1
b0
1
b15
1
b14
1
b13
1
b12
1
b11
1
b10
1
b9
1
b8
1
b7
1
b6
1
b5
1
b4
1
b3
1
b2
1
b1
1
b0
1
b15
1
b14
1
b13
1
b12
1
b11
1
b10
1
b9
1
b8
1
b7
1
b6
1
b5
1
b4
1
b3
1
b2
1
b1
1
b0
1
b15
1
b14
1
b13
1
b12
1
b11
1
b10
1
b9
1
b8
1
b7
1
b6
1
b5
1
b4
1
b3
1
b2
1
b1
1
b0
1
Address:
Bit:
Value after reset:
Address:
Bit:
Value after reset:
Address:
Bit:
Value after reset:
Address:
Bit:
Value after reset:
Each of GRA and GRB is a 16-bit readable/writable register that can function as either an output-
compare register or an input-capture register. The function is selected with TRGIOR.
When a general register is used as an output-compare register, its value is constantly compared
with the TRGCNT value. When the two values match (a compare match), the corresponding flag
(the IMFA or IMFB bit) in TRGSR is set to 1. A compare match output can be selected in
TRGIOR.
When a general register is used as an input-capture register, an external input-capture signal is
detected and the current TRGCNT value is stored in the general register. The corresponding flag
(the IMFA or IMFB bit) in TRGSR is set to 1. The edge of the input-capture signal is selected in
TRGIOR. The setting of TRGIOR is ignored in PWM mode.