Datasheet

Section 17 Timer RE
REJ09B0465-0300 Rev. 3.00 Page 627 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
17.6 Usage Notes
(1) Starting and Stopping Counting Process
The timer RE includes a TSTART bit that directs the start or stop of the counting process, and a
TCSTF bit that indicates that the counting process has started or stopped.
Setting the TSTART bit to 1 causes the timer RE to start counting and assigns 1 to the TCSTF bit.
From the time the TSTART bit is set to 1 and to the time the TCSTF bit turns 1, a maximum of 2
cycles of count sources are required. During this time period, the timer RE related registers*, with
the exception of the TCSTF bit, should not be accessed.
Similarly, clearing the TSTART bit to 0 causes the timer RE to stop counting, and assigns 0 to the
TCSTF bit. From the time the TSTART bit is set to 0 and to the time the TCSTF bit turns 0, the
timer RE related registers*, with the exception of the TCSTF bit, should not be accessed.
Note: Timer RE related registers: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2,
and TRECSR
(2) Register Settings of Timer RE
The following registers and bits should be written when the timer RE is stopped.
The condition "timer RE stopped" refers to the condition in which both the TSTART and TCSTF
bits in TRECR1 are 0. Set TRECR2 at the end of setting the above registers and bits (before the
timer RE counting process is started).
• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2
• Bits H12_H24 bit, PM, and INT in TRECR1
• Bits RCS0 to RCS3 in TRECSR
(3) Sampling Circuit for Noise Canceler in φ Subclock Signal
When selecting the φsub as the clock source for the timer RE, always enable the sampling circuit
with the SUBNC[1:0] bits in SYSCCR. For details of the SUBNC[1:0] bits, see section 5.2.2,
System Clock Control Register (SYSCCR).
(4) Restrictions on Clock Selection in Output Compare Mode
In output compare mode, do not select the φsub clock as the clock source for the timer if the CPU
is in φloco mode.