Datasheet

Section 17 Timer RE
REJ09B0465-0300 Rev. 3.00 Page 623 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
17.4 Operation of Output Compare Mode
Writing 0 to the RCS3 bit in TRECSR sets the timer RE in output compare mode and causes it to
operate as a counter provided with an 8-bit compare match function. Four count sources can be
selected. When used in output compare mode, the timer RE should be initialized. When timer RE
is initialized, first select the output-compare mode through the RCS3 bit in TRECSR and then
perform the initial setting procedure shown in figure 17.3.
The count source selected by the RCS1 and RCS0 bits is divided into two and counted with an 8-
bit counter. Setting 1 to the RCS2 bit in TRECSR causes the count source divided into two to be
counted with a 4-bit counter, and the 8-bit counter counts overflows of the 4-bit counter.
TREMIN sets a compare value. By reading TRESEC, it is possible to read values from the 8-bit
counter. In this mode, TREHR or TREWK is not used. Setting bits RCS6 to RCS4 in TRECSR to
B'011 and setting the TOENA bit in TRECR1 to 1 produces toggle output from the TREO pin
each time the value of the 8-bit counter matches the value of TREMIN (initial value: low output).
Also, by setting the COMIE bit in TRECR2 to 1, it is possible to generate a compare match
interrupt request. The counter, using the TSTART bit in TRECR1, controls the start/stop of
counter operation.
Figure 17.6 shows a block diagram of output compare mode; figure 17.7 shows an operation
example.