Datasheet

Section 17 Timer RE
REJ09B0465-0300 Rev. 3.00 Page 615 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
17.2.6 Timer RE Control Register 2 (TRECR2)
Address:
Bit:
Value after reset:
b7
⎯
0
b6
⎯
0
b5
COMIE
0
b4
WKIE
0
b3
DYIE
0
b2
HRIE
0
b1
MNIE
0
b0
SEIE
0
H'FFFFAD
Bit Symbol Bit Name Description R/W
7, 6 ⎯ Reserved These bits are read as 0. The write value should be 0. ⎯
5 COMIE Compare-match
interrupt enable
0: Disables a compare-match interrupt
1: Enables a compare-match interrupt
This bit should be 0 in realtime clock mode.
R/W
4 WKIE Week periodic
interrupt enable
0: Disables a week periodic interrupt
1: Enables a week periodic interrupt
This bit should be 0 in output-compare mode.
R/W
3 DYIE Day periodic
interrupt enable
0: Disables a day periodic interrupt
1: Enables a day periodic interrupt
This bit should be 0 in output-compare mode.
R/W
2 HRIE Hour periodic
interrupt enable
0: Disables an hour periodic interrupt
1: Enables an hour periodic interrupt
This bit should be 0 in output-compare mode.
R/W
1 MNIE Minute periodic
interrupt enable
0: Disables a minute periodic interrupt
1: Enables a minute periodic interrupt
This bit should be 0 in output-compare mode.
R/W
0 SEIE Second periodic
interrupt enable
0: Disables a second periodic interrupt
1: Enables a second periodic interrupt
This bit should be 0 in output-compare mode.
R/W
Notes: 1. When using interrupts, this register should be set last after other registers are set.
2. The COMIE bit should be set when counting operation is stopped.
3. Bits WKIE, DYIE, HRIE, MNIE, and SEIE should be set when timer RE operation is
stopped.
TRECR2 controls timer RE periodic interrupts of weeks, days, hours, minutes, and seconds in
realtime clock mode. Enabling interrupts of weeks, days, hours, minutes, and seconds sets the
interrupt request flag to 1 in the timer RE interrupt flag register (TREIFR) when an interrupt
occurs. It also controls a compare-match interrupt when output-compare mode is used.