Datasheet

Section 17 Timer RE
Page 608 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
17.2.1 Timer RE Second Data Register/Counter Data Register (TRESEC)
Address:
Bit:
Value after reset:
b7
BSY
⎯
b6
SC12
⎯
b5
SC11
⎯
b4
SC10
⎯
b3
SC03
⎯
b2
SC02
⎯
b1
SC01
⎯
b0
SC00
⎯
H'FFFFA8
• Realtime clock mode
Bit Symbol Bit Name Description R/W
7 BSY Timer RE busy This bit is set to 1 when the timer RE is updating (calculating)
the values of second, minute, hour, and day-of-week data
registers. When this bit is 0, the values of second, minute,
hour, and day-of-week data registers must be adopted.
R
6 SC12 R/W
5 SC11 R/W
4 SC10
Counting ten's
position of
seconds
Counts on 0 to 5 for 60-second counting.
R/W
3 SC03 R/W
2 SC02 R/W
1 SC01 R/W
0 SC00
Counting one's
position of
seconds
Counts on 0 to 9 once per second. When a carry is
generated, 1 is added to the ten's position.
R/W
• Output-compare mode
Bit Symbol Bit Name Description R/W
7 BSY R
6 SC12 R/W
5 SC11 R/W
4 SC10 R/W
3 SC03 R/W
2 SC02 R/W
1 SC01 R/W
0 SC00
⎯ Used as an 8-bit register for reading the counter data.
The counter value is retained when counting is stopped.
This register is initialized to H’00 with a compare-match.
R/W
TRESEC counts the BCD-coded second value in realtime clock mode. TRESEC is incremented
from decimal 00 to 59. TRESEC is used as an 8-bit register for reading the counter data in output-
compare mode.