Datasheet

Section 16 Timer RD
Page 604 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Compare match
signal B0
φ
FTIOB0 pin
TRDOCR
write signal
Set value
Bit
TRDOCR
00000110
76543210
TOD1 TOC1 TOB1 TOA1 TOD0 TOC0 TOB0 TOA0
Expected
output
Remains high because the 1 writing to TOB has priority
TRDOCR has been set to H'06. Compare match B0 and compare match C0 are used. The FTIOB0 pin is in the 1
output state, and is set to the toggle output or the 0 output by compare match B0.
When BCLR#2, @TRDOCR is executed to clear the TOC0 bit (the FTIOC0 signal is low) and compare match B0
occurs at the same timing as shown below, the H'02 writing to TRDOCR has priority and compare match B0 does
not drive the FTIOB0 signal low; the FTIOB0 signal remains high.
BCLR#2, @TRDOCR
(1) TRDOCR read operation: Read H'06
(2) Modify operation: Modify H'06 to H'02
(3) Write operation to TRDOCR: Write H'02
Figure 16.73 When Compare Match and Bit Manipulation Instruction to TRDOCR
Occur at the Same Timing