Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 603 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(9) Notes on Setting Reset Synchronous PWM Mode/Complementary PWM Mode
When bits CMD1 and CMD0 in TRDFCR are set, note the following:
• Write bits CMD1 and CMD0 while TRDCNT_1 and TRDCNT_0 are halted.
• Changing the settings of reset synchronous PWM mode to complementary PWM mode or vice
versa is disabled. Set reset synchronous PWM mode or complementary PWM mode after the
normal operation (bits CMD1 and CMD0 are cleared to 0) has been set.
(10) Note on Writing to the TOA0 to TOD0 Bits and the TOA1 to TOD1 Bits in TRDOCR
The TOA0 to TOD0 bits and the TOA1 to TOD1 bits in TRDOCR decide the value of the FTIO
pin, which is output until the first compare match occurs. Once a compare match occurs and this
compare match changes the values of FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 output, the
values of the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pin output and the values read from the
TOA0 to TOD0 and TOA1 to TOD1 bits may differ. Moreover, when the writing to TRDOCR
and the generation of the compare match A0 to D0 and A1 to D1 occur at the same timing, the
writing to TRDOCR has the priority. Thus, output change due to the compare match is not
reflected to the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pins. Therefore, when bit
manipulation instruction is used to write to TRDOCR, the values of the FTIOA0 to FTIOD0 and
FTIOA1 to FTIOD1 pin output may result in an unexpected result. When TRDOCR is to be
written to while compare match is operating, stop the counter once before accessing to TRDOCR,
read the port 6 state to reflect the values of FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 output,
to TOA0 to TOD0 and TOA1 to TOD1, and then restart the counter. Figure 16.73 shows an
example when the compare match and the bit manipulation instruction to TRDOCR occur at the
same timing.