Datasheet

Section 16 Timer RD
Page 602 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(8) Conflict between GR Write and Input Capture
If an input capture signal is generated in the T
2
state of a GR write cycle, the input capture
operation has priority and the write to GR is not performed. Figure 16.72 shows the timing in this
case.
φ
WGR
(internal write signal)
GR address
GR write cycle
TRDCNT
N
T
1 T 2
Input capture signal
Address bus
GR M
GR write data
Figure 16.72 Conflict between GR Write and Input Capture