Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 599 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(5) Conflict between TRDCNT Write and Overflow/Underflow
If overflow/underflow occurs in the T
2
state of a TRDCNT write cycle, TRDCNT write has
priority without an increment operation. At this time, the OVF flag is set to 1. Figure 16.69 shows
the timing in this case.
φ
WTRDCNT
(internal write signal)
TRDCNT address
TRDCNT write cycle
TRDCNT H'FFFF
M
T
1 T2
TRDCNT input clock
TRDCNT write data
Overflow signal
OVF
Figure 16.69 Conflict between TRDCNT Write and Overflow