Datasheet

Section 16 Timer RD
Page 594 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
16.4 Interrupt Sources
There are three kinds of timer RD interrupt sources; input capture/compare match, overflow, and
underflow. An interrupt is requested when the corresponding interrupt request flag is set to 1 while
the corresponding interrupt enable bit is set to 1.
16.4.1 Status Flag Set Timing
(1) IMF Flag Set Timing
The IMF flag is set to 1 by the compare match signal that is generated when the GR matches with
the TRDCNT. The compare match signal is generated at the last state of matching (timing to
update the counter value when the GR and TRDCNT match). Therefore, when the TRDCNT and
GR matches, the compare match signal will not be generated until the TRDCNT input clock is
generated. Figure 16.62 shows the timing to set the IMF flag.
φ
TRDCNT
input clock
Compare match
signal
IMF
TRDCNT N
N+1
GR
N
Figure 16.62 IMF Flag Set Timing when Compare Match Occurs