Datasheet

Section 16 Timer RD
Page 586 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(2) Output Disable Timing of Timer RD by External Trigger
When TRDOI is selected for inputs and low level is input to TRDOI, the master enable bit in
TRDOER1 is set to 1 and the output of timer RD will be disabled.
TRDOI
TRDOER1
Timer RD
output pin
Timer RD output
I/O port
Timer RD output
I/O port
0
1
φ
Figure 16.51 Example of Output Disable Timing of Timer RD by External Trigger
(3) Output Inverse Timing by TRDFCR
The output level can be inverted by inverting the OLS1 and OLS0 bits in TRDFCR in reset
synchronous PWM mode or complementary PWM mode. Figure 16.52 shows the timing.
φ
Timer RD
output pin
Address bus TRDFCR address
Inverted
TRDFCR
T
1 T 2
Figure 16.52 Example of Output Inverse Timing of Timer RD by Writing to TRDFCR