Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 581 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
GRA Nn
TRDCNT
Compare match
signal
Buffer transfer
signal
n
n+1
GRC
N
φ
Figure 16.45 Example of Compare Match Timing for Buffer Operation
Figure 16.46 shows an operation example in which GRA has been designated as an input capture
register, and buffer operation has been designated for GRA and GRC.
Counter clearing by input capture B has been set for TRDCNT, and falling edges have been
selected as the FTIOB pin input capture input edge. And both rising and falling edges have been
selected as the FTIOA pin input capture input edge.
As buffer operation has been set, when the TRDCNT value is stored in GRA upon the occurrence
of input capture A, the value previously stored in GRA is simultaneously transferred to GRC. The
transfer timing is shown in figure 16.47.