Datasheet

Section 16 Timer RD
Page 574 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Figure 16.37 is an example when non-overlapped pulses are output on pins FTIOA0 and FTIOB0.
In this example, TRDCNT_0 functions as a periodic counter which is cleared on compare match
A0 (bits CCLR2 to CCLR0 in TRDCR_0 are set to B'001), and PWM3 mode is selected (bit
PWM3 in TRDFCR is cleared to 0). The cycle of the pulse is arbitrary.
TRDCNT value
H'FFFF
H'0000
GRA_0
GRA_1
GRB_0
GRB_1
FTIOA0
FTIOB0
Counter cleared on GRA_0
compare match
Time
Figure 16.37 Example of Non-Overlap Pulses