Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 571 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
16.3.8 PWM3 Mode Operation
In PWM3 mode, single-phase PWM waveforms can be output using TRDCNT_0. The waveform
does not overlap its counter-phase waveform.
When the PWM3 mode is selected, the FTIOA0 and FTIOB0 pins are automatically set to output
pins for the PWM function using TRDCNT_0 regardless of the TRDPMR value. The waveform is
output on a GRA_0, GRA_1, GRB_0, or GRB_1 compare match according to bits TOA0 and
TOB0 in TRDOCR regardless of the TRDIORA and TRDIORC settings.
• When TOA0 = 0, 1 is output on a compare match of GRA_1 and 0 is output on a compare
match of GRA_0 on the FTIOA0 pin.
• When TOA0 = 1, 0 is output on a compare match of GRA_1 and 1 is output on a compare
match of GRA_0 on the FTIOA0 pin.
• When TOB0 = 0, 1 is output on a compare match of GRB_1 and 0 is output on a compare
match of GRB_0 on the FTIOB0 pin.
• When TOB0 = 1, 0 is output on a compare match of GRB_1 and 1 is output on a compare
match of GRB_0 on the FTIOB0 pin.
Table 16.9 lists the correspondence between pin functions and GR registers, figure 16.35 shows a
block diagram in PWM3 mode, and figure 16.36 shows a flowchart of setting in PWM3 mode.
When the buffer operation is used, set TRDMDR. The timer input/output pins, which are not used
in PWM3 mode, can be used as general port pins. When the buffer operation is not set, since GRC
or GRD is not used, a compare match interrupt can be generated when GRC or GRD matches with
TRDCNT_1.