Datasheet

Section 16 Timer RD
Page 570 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
When the counter is incremented or decremented, the IMFA flag of channel 0 is set to 1, and when
the register is underflowed, the UDF flag of channel 0 is set to 1. After buffer operation has been
designated for GR, the value in the buffer registers is transferred to GR when the counter is
incremented by compare match A0 or when TRDCNT_1 is underflowed. In complementary PWM
mode, the OVF flag is not set to 1 at the timing that the counter value changes from H'FFFF to
H'0000 as shown in figure 16.34.
(3) Setting GR Value in Complementary PWM Mode
To set the general register (GR) or modify GR during operation in complementary PWM mode,
see the following notes.
1. Initial value
⎯ H'0000 to T – 1 (T: Initial value of TRDCNT_0) must not be set for the initial value.
⎯ GRA_0 – (T – 1) or more must not be set for the initial value.
⎯ When using buffer operation, the same values must be set in the buffer registers and
corresponding general registers.
2. Modifying the setting value
⎯ Use the buffer operation to change the GR value. If the GR value is changed by writing to
it directly, the intended waveform may not be output.
⎯ Do not change settings of GRA_0 during operation.